1. Field of the Invention
Example embodiments of the present invention relate to a precursor, for example, a Te precursor, for lower temperature deposition, a thin layer, for example, a Te-containing chalcogenide thin layer, prepared by employing the precursor; and a method of preparing the thin layer, and for example, to a precursor for lower temperature deposition containing Te, a 15-group compound and/or a 14-group compound; a chalcogenide thin layer doped with a 15-group compound and/or a 14-group compound and prepared at lower temperature by employing the precursor, and a method of preparing the thin layer. Also, example embodiments of the present invention relate to a phase-change memory device including a phase-change layer formed by employing the precursor.
2. Description of the Related Art
A phase-change material is a material that may have a crystalline state or an amorphous state, depending on temperature. The crystalline state has lower resistance than the amorphous state and has an ordered regular atomic arrangement. The crystalline state and the amorphous state may be reversible. That is, the crystalline state may be changed to the amorphous state and the amorphous state may be changed back into the crystalline state. A phase-change random access memory device (PRAM) is a memory device applying the characteristics that a phase-change material has reversible states and distinguishable resistances.
The general form of a PRAM may include a phase-change layer electrically connected to a source or a drain area of a transistor through a contact plug. Operation as a memory may be performed by employing the difference in resistance due to the change of crystal structure in the phase-change layer. FIG. 1 shows the general form of PRAM according to the conventional art. Hereinafter, referring to FIG. 1, the general structure of a conventional PRAM is described.
Referring to FIG. 1, on the transistor substrate 10, a first impurity area 11a and a second impurity area 11b may be formed, and a gate insulating layer 12 and a gate electrode layer 13 may be formed in contact with the two impurity areas. The first impurity area 11a may be referred to a source and the second impurity area 11b may be referred to a drain.
On the first impurity area 11a, the gate electrode layer 13 and on the second impurity area 11b, the insulating layer 15 may be formed, and a contact plug 14 may be formed in contact with the second impurity area 11b, penetrating the insulating layer 15. On the contact plug 14, a lower electrode 16 may be formed, and on the lower electrode 16, the phase-change layer 17 and the upper electrode 18 may be formed.
A technique of storing data in the PRAM having the structure described above may be as follows. Joule heat is generated at the contact area of the lower electrode 16 and the phase-change layer 17 by the electric current applied through the second impurity area 11b and the lower electrode 16. Data is stored by changing the crystal structure of the phase-change layer 17 with the Joule heat. That is, the crystal structure of the phase-change layer 17 is changed into a crystalline state or an amorphous state by changing an applied electric current. Accordingly, the previous data stored can be distinguished since the resistance is changed in response to the change between the crystalline state and the amorphous state.
Various types of phase-change material that can be applied to memory devices are known, and a representative example thereof is GST (GeSbTe) based alloy. Transistor memory devices including various types of chalcogenide material layers are known.
It may be beneficial to decrease a consumed electric current value in order to improve the performance of a memory device. For a PRAM that includes a GST layer, a phase-change material being used frequently, the reset current value, e.g., the current value for transition from crystalline state to amorphous state is high.
FIG. 2 is a graph showing heating temperatures for the Reset/Set Programming of a memory device that uses GST (Ge2Sb2Te5) in a phase-change layer.
Referring to FIG. 2, it may be seen that crystallization can be achieved by keeping the temperature lower than the melting point for a period of time, for set programming for GST, e.g., changing the amorphous state into the crystalline state. It may be seen that temperature should be elevated to almost the melting point (Tm) and then cooled, for reset programming, e.g., changing the crystalline state into the amorphous state. The current needed to elevate the temperature to the melting point (Tm) is relatively high. As a result, there may be a limit in realizing higher integrated memory devices.